A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

This paper presents a Q-band image-rejection receiver using 65 nm CMOS technology. For high ratio (IMRR), the employs Hartley architecture which consists of low-noise amplifier, two down-conversion mixers, 90° hybrid coupler, and IF baluns. In addition, fundamental voltage-controlled oscillator (VCO) frequency divider chain divided by 256 are integrated into for LO. A charge injection technique is employed in mixers to reduce DC power while maintaining conversion gain linearity. The VCO adopts cross-coupled topology secure stable oscillation with output Q-band. composed an injection-locked (ILFD) multi-stage current-mode logic (CML) achieve division 256, facilitates LO signal locking external phase-locked loop. An inductive peaking ILFD widen range. exhibits peak 16.4 dB at 43 GHz. IMRR no less than 35.6 dBc frequencies from 1.5 5